The legacy architecture to which the invention is applied includes SIMD processor arrays that are configured with a ring or a toroidal topology. In a rectangular SIMD array, the top (hereinafter also referred as north) and bottom (hereinafter also referred as south) boundaries are coupled to provide wrap-around in the North-South (NS) direction, and/or the right (hereinafter also referred as east) and left (hereinafter also referred as west) boundaries are coupled to provide wrap-around in the East-West (EW) direction. The purpose of this wrap-around is to allow processing with fewer edge effects, and on occasions to allow data that is shifted “off boundary” to be recovered. There are also algorithms, such as resampling, where shifting across a boundary provides a significant speedup.
Although it is difficult to quantify the improvement due to array wrap-around, programmers of the legacy architecture have traditionally insisted upon this feature as a necessary characteristic of the array. On the other hand, system implementation issues that arise from supporting this feature have been non-trivial. To avoid large propagation distances and loads for wrapped signals, it has been necessary (at both board and chip level) to interleave rows and columns of chips or of PE Groups (PEGs). This has led to very messy signal routing within board/chip layout solutions.
The present invention provides a solution, wherein a flat array is effectively “folded” to co-locate boundaries for making the wrap around connections. Yet further, a “Layered PEG” provides a building block for creating folded arrays.